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w wm8718 24 bit differential stereo dac with volume control wolfson microelectronics plc to receive regular email updates, sign up at http://www.wolfsonmicro.com/enews/ production data, november 2006, rev 4.3 copyright ? 2006 wolfson microelectronics pl c description the wm8718 is a high performance differential stereo dac designed for audio applications such as dvd, home theatre systems and digital tv. the wm8718 supports pcm data input word lengths from 16 to 32-bits and sampling rates up to 192khz. the wm8718 consists of a serial interface port, digital interpolation filters, multi-bit sigma delta modulators and differential stereo dac in a small 20-lead ssop package or 24-lead qfn package. the wm8718 includes a digitally controllable mute, an attenuate function and zero flag output for each channel. the 3-wire serial control port provides access to a wide range of features including on-chip mute, attenuation and phase reversal. the wm8718 is an ideal device to interface to ac-3 ? , dts ? , and mpeg audio decoders for surround sound applications, or for use in dvd players including those supporting dvd-a. features ? 24 bit stereo dac ? fully differential voltage outputs ? audio performance - 111db snr (?a? weighted @ 48khz) dac - -100db thd ? dac sampling frequency: 8khz - 192khz ? 3 wire serial control interface ? programmable audio data interface modes - i 2 s, left, right justified, dsp - 16/20/24/32 bit word lengths ? independent digital volume control on each channel with 127.5db range in 0.5db steps ? independent zero flag outputs ? 3.0v - 5.5v supply operation ? 20-lead ssop package or 24-lead qfn package applications ? cd, dvd, and dvd-audio players ? home theatre systems ? professional mixing desks block diagram audio interface att/ mute control interface bckin voutln voutrn sigma delta modulator lrcin din att/ mute sigma delta modulator digital filters mclk sclk sdin latch vmid dac dac vrefn vrefp voutrp voutlp zerofl zerofr agnd avdd dgnd dvdd w wm8718
wm8718 production data w pd rev 4.3 november 2006 2 table of contents description ............................................................................................................1 features..................................................................................................................1 applications ..........................................................................................................1 block diagram ......................................................................................................1 table of contents ..............................................................................................2 pin configuration ? 20 lead ssop ..................................................................3 ordering information ? 20 lead ssop..........................................................3 pin configuration ? 24 lead qfn.....................................................................4 ordering information ? 24 lead qfn ............................................................4 pin description ? 20 lead ssop........................................................................5 pin description ? 24 lead qfn ..........................................................................6 absolute maximum ratings..............................................................................7 dc electrical characteristics .....................................................................8 electrical characteristics ...........................................................................8 terminology ................................................................................................................. 9 master clock timing .................................................................................................10 digital audio interface timings ...........................................................................10 3-wire serial control interface timing ...........................................................11 internal power on reset circuit ...............................................................12 device description ............................................................................................14 introduction ...............................................................................................................14 clocking schemes .....................................................................................................14 digital audio interface ...........................................................................................14 audio data sampling rates.....................................................................................16 register map ...............................................................................................................18 digital filter characteristics.............................................................................24 dac filter responses...............................................................................................24 digital de-emphasis characteristics ........................................................25 typical performance.......................................................................................26 applications information ..............................................................................27 recommended external components ? 20 lead ssop ...................................27 recommended external components ? 24 lead qfn .....................................28 recommended external components values .................................................28 recommended analogue low pass filter for pcm data format (optional)..................................................................................................................... .29 package dimensions ? 20 lead ssop............................................................30 package dimensions ? 24 lead qfn ..............................................................31 important notice ...............................................................................................32 address: ....................................................................................................................... .32
wm8718 production data w pd rev 4.3 november 2006 3 pin configuration ? 20 lead ssop sclk sdin z e r o f r d i n agnd dgnd lrcin v o u t l p voutln l a t c h voutrn wm8718 16 15 14 20 19 18 17 5 6 7 1 2 3 4 vmid vrefp avdd dvdd 13 12 11 8 9 10 voutrp mclk bckin vrefn z e r o f l ordering information ? 20 lead ssop device temperature range package moisture sensitivity level peak soldering temperature wm8718seds -25 to +85 o c 20-lead ssop (pb-free) msl1 260c wm8718seds/r -25 to +85 o c 20-lead ssop (pb-free, tape and reel) msl1 260c note: reel quantity = 2,000
wm8718 production data w pd rev 4.3 november 2006 4 pin configuration ? 24 lead qfn ordering information ? 24 lead qfn device temperature range package moisture sensitivity level peak soldering temperature wm8718gefl/v -25 to +85 o c 24-lead qfn (pb-free) msl3 260c wm8718gefl/rv -25 to +85 o c 24-lead qfn (pb-free, tape and reel) msl3 260c note: reel quantity = 3,500
wm8718 production data w pd rev 4.3 november 2006 5 pin description ? 20 lead ssop pin name type description 1 lrcin digital input pcm dac sample rate clock input 2 dvdd supply positive digital supply 3 dgnd supply ground digital supply 4 avdd supply positive analogue supply 5 vrefp supply positive dac reference supply 6 vrefn supply negative dac reference supply 7 agnd supply ground analogue supply 8 vmid analogue output mid rail decoupling point 9 voutrp analogue output right channel dac output positive 10 voutrn analogue output right channel dac output negative 11 voutln analogue output left channel dac output negative 12 voutlp analogue output left channel dac output positive 13 latch digital input p.u. serial control load input 14 sdin digital input serial control data input 15 sclk digital input p.d. serial control data input clock 16 zerofr digital output (open drain) infinite zero detect flag for right channel 17 zerofl digital output (open drain) infinite zero detect flag for left channel 18 mclk digital input master clock input 19 bclkin digital input pcm audio data bit clock input 20 din digital input pcm serial audio data input note: digital input pins have schmitt trigger input buffers. pins marked `p.u.` or `p.d.` have an internal pull-up or pull-down resis tor.
wm8718 production data w pd rev 4.3 november 2006 6 pin description ? 24 lead qfn pin name type description 1 dvdd supply positive digital supply 2 dgnd supply ground digital supply 3 avdd supply positive analogue supply 4 vrefp supply positive dac reference supply 5 vrefn supply negative dac reference supply 6 agnd supply ground analogue supply 7 vmid analogue output mid rail decoupling point 8 voutrp analogue output right channel dac output positive 9 voutrn analogue output right channel dac output negative 10 voutln analogue output left channel dac output negative 11 voutlp analogue output left channel dac output positive 12 nc no connect no connect 13 nc no connect no connect 14 latch digital input p.u. serial control load input 15 sdin digital input serial control data input 16 sclk digital input p.d. serial control data input clock 17 zerofr digital output (open drain) infinite zero detect flag for right channel 18 nc no connect no connect 19 zerofl digital output (open drain) infinite zero detect flag for left channel 20 mclk digital input master clock input 21 bclkin digital input pcm audio data bit clock input 22 din digital input pcm serial audio data input 23 lrcin digital input pcm dac sample rate clock input 24 nc no connect no connect note: 1. digital input pins have schmitt trigger input buffers. pins marked `p.u.` or `p.d.` have an internal pull-up or pull-down resistor. 2. it is recommended that the qfn ground paddle should be connected to analogue ground on the application pcb.
wm8718 production data w pd rev 4.3 november 2006 7 absolute maximum ratings absolute maximum ratings are stress ratings only. permanent damage to the device may be caused by continuously operating at or beyond these limits. device functional operating limits and guaranteed performance specifications are given under electrical characteristics at the test conditions specified. esd sensitive device. this device is manufactured on a cmos process. it is therefore generically susceptible to damage from excessive static voltages. proper esd precautions must be taken during handling and storage of this device. wolfson tests its package types according to ipc/jedec j-std-020b for moisture sensitivity to determine acceptable storage conditions prior to surface mount assembly. these levels are: msl1 = unlimited floor life at <30 c / 85% relative humidity. not normally stored in moisture barrier bag. msl2 = out of bag storage for 1 year at <30 c / 60% relative humidity. supplied in moisture barrier bag. msl3 = out of bag storage for 168 hours at <30 c / 60% relative humidity. supplied in moisture barrier bag. the moisture sensitivity level for each package type is specified in ordering information. condition min max digital supply voltage (dvdd) -0.3v +7v analogue supply voltage (avdd) -0.3v +7v voltage range digital inputs dgnd -0.3v vdd +0.3v master clock frequency 37mhz operating temperature range, t a -25 c +85 c storage temperature after soldering -65 c +150 c
wm8718 production data w pd rev 4.3 november 2006 8 dc electrical characteristics parameter symbol test conditions min typ max unit digital supply range dvdd 3.0 5.5 v analogue supply range avdd 3.0 5.5 v ground agnd, dgnd 0 v difference dgnd to agnd -0.3 0 +0.3 v avdd = 3.3v 0.191 1 19 ma supply current avdd = 5v 0.191 1 22 ma dvdd = 3.3v 160 ua 7.1 ma supply current dvdd = 5v 160 ua 8.3 ma notes: 1. this value represents the current usage when there are no switching digital inputs, mclk is applied and the chip is in power down mode 2. digital supply dvdd must never be more than 0.3v greater than avdd. electrical characteristics test conditions avdd = 5v, dvdd = 3.3v, agnd, dgnd = 0v, t a = +25 o c, fs = 48khz, mclk = 256fs unless otherwise stated. parameter symbol test conditions min typ max unit digital logic levels (ttl levels) input low level v il 0.8 v input high level v ih 2.0 v output low v ol i ol = 1ma agnd + 0.3v v output high v oh i oh = 1ma dvdd ? 0.3v v analogue reference levels reference voltage vmid avdd/2 - 50mv avdd/2 avdd/2 + 50mv v potential divider resistance r vmid 8.7 k ? dac output (load = 10k ? 50pf) snr (note 1,2,3) a-weighted, @ fs = 48khz 105 111 db snr (note 1,2,3) a-weighted @ fs = 96khz 109 db snr (note 1,2,3) a-weighted @ fs = 192khz 109 db snr (note 1,2,3) a-weighted, @ fs = 48khz avdd = 3.3v 105 db snr (note 1,2,3) a-weighted @ fs = 96khz avdd = 3.3v 102 db snr (note 1,2,3) non ?a? weighted @ fs = 48khz 108 db thd (note 1,2,3) 1khz, 0dbfs -100 -80 db thd+n (dynamic range, note 2) 1khz, -60dbfs 105 111 db dac channel separation 100 db
wm8718 production data w pd rev 4.3 november 2006 9 test conditions avdd = 5v, dvdd = 3.3v, agnd, dgnd = 0v, t a = +25 o c, fs = 48khz, mclk = 256fs unless otherwise stated. parameter symbol test conditions min typ max unit analogue output levels load = 10k ? , 0dbfs 2.0 v rms differential output level load = 10k ? , 0dbfs, (avdd = 3.3v) 1.32 v rms gain mismatch channel-to-channel 1 %fsr to midrail or a.c. coupled 1 k ? minimum resistance load to midrail or a.c. coupled (avdd = 3.3v) 600 ? maximum capacitance load 5v or 3.3v 100 pf output d.c. level (avdd- gnd)/2 v power on reset (por) por threshold 2.0 v notes: 1. ratio of output level with 1khz full scale input, to the output level with all zeros into the digital input, over a 20hz to 20khz bandwidth. 2. all performance measurements done with 20khz low pass filter, and where noted an a-weight filter. failure to use such a filter will result in higher thd+n and lower snr and dynamic range readings than are found in the electrical characteristics. the low pass filter removes out of band noise; although it is not audible it may affect dynamic specification values. 3. vmid decoupled with 10uf and 0.1uf capacitors (smaller values may result in reduced performance). terminology 1. signal-to-noise ratio (db) - snr is a measure of the difference in level between the full-scale output and the output with a zero signal applied. (no auto-zero or automute function is employed in achieving these results). 2. dynamic range (db) - dnr is a measure of the difference between the highest and lowest portions of a signal. normally a thd+n measurement at 60db below full scale. the measured signal is then corrected by adding the 60db to it. (e.g. thd+n @ -60db= -32db, dr= 92db). 3. thd+n (db) - thd+n is a ratio, of the rms values, of (noise + distortion)/signal. 4. stop band attenuation (db) - is the degree to which the frequency spectrum is attenuated (outside audio band). 5. channel separation (db) - also known as cross talk. this is a measure of the amount one channel is isolated from the other. normally measured by sending a full-scale signal down one channel and measuring the other. 6. pass-band ripple ? any variation of the frequency response in the pass-band region.
wm8718 production data w pd rev 4.3 november 2006 10 master clock timing mclk t mclkl t mclkh t mclky figure 1 master clock timing requirements test conditions avdd = 5v, dvdd = 3.3v, agnd, dgnd = 0v, t a = +25 o c, fs = 48khz, mclk = 256fs unless otherwise stated. parameter symbol test conditions min typ max unit master clock timing information mclk master clock pulse width high t mclkh 13 ns mclk master clock pulse width low t mclkl 13 ns mclk master clock cycle time t mclky 26 ns mclk duty cycle 40:60 60:40 digital audio interface timings bckin lrcin t bch t bcl t bcy din t lrsu t ds t lrh t dh figure 2 digital audio data timing test conditions avdd = 5v, dvdd = 3.3v, agnd, dgnd = 0v, t a = +25 o c, fs = 48khz, mclk = 256fs unless otherwise stated. parameter symbol test conditions min typ max unit audio data input timing information bckin cycle time t bcy 40 ns bckin pulse width high t bch 16 ns bckin pulse width low t bcl 16 ns lrcin set-up time to bckin rising edge t lrsu 8 ns lrcin hold time from bckin rising edge t lrh 8 ns din set-up time to bckin rising edge t ds 8 ns din hold time from bckin rising edge t dh 8 ns
wm8718 production data w pd rev 4.3 november 2006 11 3-wire serial control interface timing latch sclk sdin t csl t dho t dsu t csh t scy t sch t scl t scs lsb t css figure 3 program register input timing - 3-wire serial control mode test conditions avdd = 5v, dvdd = 3.3v, agnd, dgnd = 0v, t a = +25 o c, fs = 48khz, mclk = 256fs unless otherwise stated. parameter symbol test conditions min typ max unit program register input information sclk rising edge to latch rising edge t scs 40 ns sclk pulse cycle time t scy 80 ns sclk pulse width low t scl 20 ns sclk pulse width high t sch 20 ns sdin to sclk set-up time t dsu 20 ns sclk to sdin hold time t dho 20 ns latch pulse width low t csl 20 ns latch pulse width high t csh 20 ns latch rising to sclk rising t css 20 ns
wm8718 production data w pd rev 4.3 november 2006 12 internal power on reset circuit figure 4 internal power on reset circuit schematic the wm8718 includes an internal power on reset circuit which is used reset the digital logic into a default state after power up. figure 4 shows a schematic of the internal por circuit. the por circuit is powered from avdd. the circuit monitors dvdd and vmid and asserts porb low if dvdd or vmid are below the minimum threshold vpor_off. on power up, the por circuit requires avdd to be present to operate. porb is asserted low until avdd and dvdd and vmid are established. when avdd, dvdd, and vmid have been established, porb is released high, all registers are in their default state and writes to the digital interface may take place. on power down, porb is asserted low whenever dvdd or vmid drop below the minimum threshold vpor_off. if avdd is removed at any time, the internal power on reset circuit is powered down and porb will follow avdd. in most applications the time required for the device to release porb high will be determined by the charge time of the vmid node. figure 5 typical power up sequence where dvdd is powered before avdd
wm8718 production data w pd rev 4.3 november 2006 13 figure 6 typical power up sequence where avdd is powered before dvdd typical por operation (typical values, not tested) symbol min typ max unit v pora 0.5 0.7 1.0 v v porr 0.5 0.7 1.1 v v pora_off 1.0 1.4 2.0 v v pord_off 0.6 0.8 1.0 v in a real application the designer is unlikely to have control of the relative power up sequence of avdd and dvdd. using the por circuit to monitor vmid ensures a reasonable delay between applying power to the device and device ready. figure 5 and figure 6 show typical power up scenarios in a real system. both avdd and dvdd must be established and vmid must have reached the threshold vporr before the device is ready and can be written to. any writes to the device before device ready will be ignored. figure 5 shows dvdd powering up before avdd. figure 6 shows avdd powering up before dvdd. in both cases, the time from applying power to device ready is dominated by the charge time of vmid. a 10uf cap is recommended for decoupling on vmid. the charge time for vmid will dominate the time required for the device to become ready after power is applied. the time required for vmid to reach the threshold is a function of the vmid resistor string and the decoupling capacitor. the resistor string has a typical equivalent resistance of 33kohm (+/-20%). assuming a 10uf capacitor, the time required for vmid to reach threshold of 1v is approx 74ms.
wm8718 production data w pd rev 4.3 november 2006 14 device description introduction the wm8718 is a high performance dac designed for digital consumer audio applications. its range of features makes it ideally suited for use in dvd players, av receivers and other high-end consumer audio equipment. wm8718 is a complete 2-channel differential stereo audio digital-to-analogue converter, including digital interpolation filter, multi-bit sigma delta with dither, switched capacitor multi-bit stereo dac. the wm8718 includes an on-chip digital volume control, configurable digital audio interface and a 3 wire mpu control interface. the wm8718 has left and right zero flag output pins, allowing the user to control external muting circuits. it is fully compatible and an ideal partner for a range of industry standard microprocessors, controllers and dsps. the software control interface may be asynchronous to the audio data interface. the control data will be re-synchronised to the audio processing internally. operation using a master clock of 256fs, 384fs, 512fs or 768fs is provided, selection between clock rates being automatically controlled. sample rates (fs) from less than 8khz to 192khz are allowed, provided the appropriate master clock is input. the audio data interface supports right justified, left justified and i 2 s (philips left justified, one bit delayed) interface formats along with a highly flexible dsp serial port interface. the device is packaged in a small 20-lead ssop. clocking schemes in a typical digital audio system there is one central clock source producing a reference clock to which all audio data processing is synchronised. this clock is often referred to as the audio system?s master clock. the external master system clock can be applied directly through the mclk input pin with no software configuration necessary for sample rate selection. note that on the wm8718, mclk is used to derive clocks for the dac path. the dac path consists of dac sampling clock, dac digital filter clock and dac digital audio interface timing. in a system where there are a number of possible sources for the reference clock, it is recommended that the clock source with the lowest jitter be used to optimise the performance of the dac. digital audio interface audio data is applied to the internal dac filters via the digital audio interface. five popular interface formats are supported: ? left justified mode ? right justified mode ? i 2 s mode ? dsp mode a ? dsp mode b all five formats send the msb first and support word lengths of 16, 20, 24 and 32 bits with the exception that 32 bit data is not supported in right justified mode. din and lrcin maybe configured to be sampled on the rising or falling edge of bckin. in left justified, right justified and i 2 s modes, the digital audio interface receives data on the din input. audio data is time multiplexed with lrcin indicating whether the left or right channel is present. lrcin is also used as a timing reference to indicate the beginning or end of the data words. the minimum number of bckins per lrcin period is 2 times the selected word length. lrcin must be high for a minimum of word length bckins and low for a minimum of word length bckins. any mark to space ratio on lrcin is acceptable provided the above requirements are met.
wm8718 production data w pd rev 4.3 november 2006 15 the wm8718 will automatically detect when data with a lrcin period of exactly 32 bckins is sent, and select 16-bit mode - overriding any previously programmed word length. word length will revert to a programmed value only if a lrcin period other than 32 bckins is detected. in dsp mode a or dsp mode b, the data is time multiplexed onto din. lrcin is used as a frame sync signal to identify the msb of the first word. the minimum number of bckins per lrcin period is 2 times the selected word length. any mark to space ratio is acceptable on lrcin provided the rising edge is correctly positioned. (see figure 10 and figure 11) left justified mode in left justified mode, the msb is sampled on the first rising edge of bckin following a lrcin transition. lrcin is high during the left data word and low during the right data word. left channel right channel lrcin bckin din 1/fs n 3 2 1 n-2 n-1 lsb msb n 3 2 1 n-2 n-1 lsb msb figure 7 left justified mode timing diagram right justified mode in right justified mode, the lsb is sampled on the rising edge of bckin preceding a lrcin transition. lrcin is high during the left data word and low during the right data word. left channel right channel lrcin bckin din 1/fs n 3 2 1 n-2 n-1 lsb msb n 3 2 1 n-2 n-1 lsb msb figure 8 right justified mode timing diagram i 2 s mode in i 2 s mode, the msb is sampled on the second rising edge of bckin following a lrcin transition. lrcin is low during the left data word and high during the right data word. left channel right channel lrcin bckin din 1/fs n 3 2 1 n-2 n-1 lsb msb n 3 2 1 n-2 n-1 lsb msb 1 bckin 1 bckin figure 9 i 2 s mode timing diagram
wm8718 production data w pd rev 4.3 november 2006 16 dsp mode a in dsp mode a, the first bit is sampled on the bckin rising edge following the one that detects a low to high transition on lrcin. no bckin edges are allowed between the data words. the word order is din left, din right. lrcin bckin din input word length (iwl) 1/fs left channel n 2 1 n-1 lsb msb n 2 1 n-1 right channel no valid data 1 bckin 1 bckin figure 10 dsp mode a timing diagram dsp mode b in dsp mode b, the first bit is sampled on the bckin rising edge, which detects a low to high transition on lrcin. no bckin edges are allowed between the data words. the word order is din left, din right. lrcin bckin din input word length (iwl) 1/fs left channel n 2 1 n-1 lsb msb n 2 1 n-1 right channel no valid data 1 figure 11 dsp mode b timing diagram audio data sampling rates the master clock for wm8718 can range from 128fs to 768fs where fs is the audio sampling frequency (lrcin), typically 32khz, 44.1khz, 48khz, 96khz or 192khz. the master clock is used to operate the digital filters and the noise shaping circuits. the wm8718 has a master clock detection circuit that automatically determines the relationship between the master clock frequency and the sampling rate (to within +/- 32 system clocks). if there is greater than 32 clo cks error, the system will default to 768fs. the master clock should be synchronised with lrcin, although the wm8718 is tolerant of phase differences or jitter on this clock. see table 1.
wm8718 production data w pd rev 4.3 november 2006 17 master clock frequency (mhz) (mclk) sampling rate (lrcin) 128fs 192fs 256fs 384fs 512fs 768fs 32khz 4.096 6.144 8.192 12.288 16.384 24.576 44.1khz 5.6448 8.467 11.2896 16.9340 22.5792 33.8688 48khz 6.144 9.216 12.288 18.432 24.576 36.864 88.2khz 11.2896 16.9344 22.5792 33.8688 unavailable unavailable 96khz 12.288 18.432 24.576 36.864 unavailable unavailable 176.4khz 22.5792 33.8688 unavailable unavailable unavailable unavailable 192khz 24.576 36.864 unavailable unavailable unavailable unavailable table 1 typical relationships between master clock frequency and sampling rate software control interface the software control interface may be operated using a 3-wire (spi-compatible) interface. in this mode, sdin is used for the program data, sclk is used to clock in the program data and latch is used to latch in the program data. the 3-wire interface protocol is shown in figure 12. latch sclk sdin a6 d6 d7 d8 a0 a1 a2 a3 a4 a5 d1 d2 d3 d4 d5 d0 figure 12 3-wire serial control interface notes: 1. a[6:0] are control address bits 2. d[8:0] are control data bits
wm8718 production data w pd rev 4.3 november 2006 18 register map wm8718 uses a total of 4 program registers, which are 16-bits long. these registers are all loaded through input pin sdin, using the 3-wire serial control mode as shown in 9. a6 a5 a4 a3 a2 a1 a0 d8 d7 d6 d5 d4 d3 d2 d1 d0 m0 0 0 0 0 0 0 0 updatel lat7 lat6 lat5 lat4 lat3 lat2 lat1 lat0 m1 0 0 0 0 0 0 1 updater rat7 rat6 rat5 rat4 rat3 rat2 rat1 rat0 m2 0 0 0 0 0 1 0 zcdinit zeroflr 0 1 0 1 0 1 0 1 pwdn deemph mut m3 0 0 0 0 0 1 1 0 1 rev bcp atc lrp fmt[1] fmt[0] iwl[1] iwl[0] address data table 2 mapping of program registers note: 1. these register bits must be written as 0 otherwise device function can not be guaranteed. register address (a3,a2,a1,a0) bits name default description [7:0] lat[7:0] 11111111 (0db) attenuation data for left channel in 0.5db steps, see table 5 0000 dacl attenuation 8 updatel 0 attenuation data load control for left channel. 0: store dacl in intermediate latch (no change to output) 1: store dacl and update attenuation on both channels. [7:0] rat[7:0] 11111111 (0db) attenuation data for right channel in 0.5db steps, see table 5 0001 dacr attenuation 8 updater 0 attenuation data load control for right channel. 0: store dacr in intermediate latch (no change to output) 1: store dacr and update attenuation on both channels. 0 mut 0 left and right dacs soft mute control. 0: no mute 1: mute 1 deemph 0 de-emphasis control. 0: de-emphasis off 1: de-emphasis on 2 pwdn 0 left and right dacs power-down control 0: all dacs running, output is active 1: all dacs in power saving mode, output muted 7 zeroflr 0 zero flag pin control. 0: channel independent 1: and of both channels on zerofl output pin 0010 mode control 8 zcdinit 0 zero cross detect control. 0: zero cross detect enabled 1: zero cross detect disabled 0011 format control [1:0] iwl[1:0] 10 input word length. 00: 16-bit mode 01: 20-bit mode 10: 24-bit mode 11: 32-bit mode(not supported in right justified mode)
wm8718 production data w pd rev 4.3 november 2006 19 register address (a3,a2,a1,a0) bits name default description [3:2] fmt[1:0] 10 audio data format select. 00: right justified mode 01: left justified mode 10: i 2 s mode 11: dsp mode 4 lrp 0 polarity select for lrcin/dsp mode select. 0: normal lrcin polarity/dsp late mode 1: inverted lrcin polarity/dsp early mode 5 atc 0 attenuator control. 0: all dacs use attenuation as programmed. 1: right channel dacs use corresponding left dac attenuation 6 bcp 0 bckin polarity 0: normal polarity 1: inverted polarity 7 rev 0 output phase reversal, see table 10 table 3 register bit descriptions attenuation control each dac channel can be attenuated digitally before being applied to the digital filter. attenuation is 0db by default but can be set between 0 and 127.5db in 0.5db steps using the 8 attenuation control bits. all attenuation registers are double latched allowing new values to be pre-latched to both channels before being updated synchronously. setting the update bit on any attenuation write will cause all pre-latched values to be immediately applied to the dac channels. register address bits label default description [7:0] lat[7:0] 11111111 (0db) attenuation data for left channel dacl in 0.5db steps. 0000 attenuation dacl 8 updatel 0 controls simultaneous update of all attenuation latches 0: store dacl in intermediate latch (no change to output) 1: store dacl and update attenuation on all channels. [7:0] rat[7:0] 11111111 (0db) attenuation data for right channel dacr in 0.5db steps. 0001 attenuation dacr 8 updater 0 controls simultaneous update of all attenuation latches 0: store dacr in intermediate latch (no change to output) 1: store dacr and update attenuation on all channels. table 4 attenuation register map note: 1. the update bit is not latched. if update=0, the attenuation value will be written to the pre-latch but not applied to the relevant dac. if update=1, all pre-latched values and the current value being written will be applied on the next input sample. 2. care should be used in reducing the attenuation as rapid large volume changes can introduce zipper noise if the zcdinit register bit has been set, (disabled).
wm8718 production data w pd rev 4.3 november 2006 20 dac output attenuation registers dacr and dacl control the left and right channel attenuation. table 9 shows how the attenuation levels are selected from the 8-bit words. dacx[7:0] attenuation level 00(hex) db (mute) 01(hex) 127.5db : : : : : : fe(hex) 0.5db ff(hex) 0db table 5 attenuation control levels mute modes figure 13 shows the application and release of mute whilst a full amplitude sinusoid is being played at 48khz sampling rate. when mute (lower trace) is asserted, the output (upper trace) begins to decay exponentially from the dc level of the last input sample. the output will decay towards v mid with a time constant of approximately 64 input samples. when mute is de- asserted, the output will restart almost immediately from the current input sample. -2.5 -2 -1.5 -1 -0.5 0 0.5 1 1.5 0 0.001 0.002 0.003 0.004 0.005 0.006 time(s) figure 13 application and release of soft mute setting the mut register bit will apply a 'soft' mute to the input of the digital filters: register address bit label default description 0010 mode control 0 mut 0 soft mute select 0: normal operation 1: soft mute both channels
wm8718 production data w pd rev 4.3 november 2006 21 de-emphasis mode setting the deemph register bit puts the digital filters into de-emphasis mode: register address bit label default description 0010 mode control 1 deemph 0 de-emphasis mode select: 0: de-emphasis off 1: de-emphasis on powerdown mode setting the pwdn register bit immediately connects all outputs to v mid and selects a low power mode. all trace of the previous input samples is removed, but all control register settings are preserved. when pwdn is cleared again the first 16 input samples will be ignored, as the fir will repeat it's power-on initialisation sequence. register address bit label default description 0010 mode control 2 pwdn 0 power down mode select: 0: normal mode 1: power down mode zero flag outputs the wm8718 has two zero flag outputs pins. the wm8718 asserts a low on the corresponding zero flag pin when a sequence of more than 1024 mid-rail signal is input to the chip. the user can use the zero flag pins to control external muting circuits if required. to simplify external circuitry there is an option to have both zero flag output?s anded internally and output on both pins. register address bit label default description 0010 mode control 7 zeroflr 0 zero flag outputs: 0: both pins enabled. 1: and of both channels to both pins. zero cross detect when the wm8718 receives updates to the volume levels it will, by default, wait for the signal to pass through mid-rail for each channel before applying the update for that particular channel. this ensures that there is minimum distortion seen on the output when the volume is changed. register address bit label default description 0010 mode control 8 zcdinit 0 zero cross detect control: 0: enabled 1: disabled selection of lrcin polarity in left justified, right justified or i 2 s modes, the lrp register bit controls the polarity of lrcin. if this bit is set high, the expected polarity of lrcin will be the opposite of that shown in figure 7, figure 8 and figure 9. note that if this feature is used as a means of swapping the left and right channels, a 1 sample phase difference will be introduced. register address bit label default description 0011 format control 4 lrp 0 lrcin polarity (normal) 0: normal lrcin polarity 1: inverted lrcin polarity table 6 lrcin polarity control in dsp modes, the lrcin register bit is used to select between early and late modes (see figure 10 and figure 11.
wm8718 production data w pd rev 4.3 november 2006 22 register address bit label default description 0011 format control 4 lrp 0 dsp format (dsp modes) 0: late dsp mode 1: early dsp mode table 7 dsp format control in dsp early mode, the first bit is sampled on the bckin rising edge following the one that detects a low to high transition on lrcin. in dsp late mode, the first bit is sampled on the bckin rising edge, which detects a low to high transition on lrcin. no bckin edges are allowed between the data words. the word order is din left, din right. attenuator control mode setting the atc register bit causes the left channel attenuation settings to be applied to both left and right channel dacs from the next audio input sample. no update to the attenuation registers is required for atc to take effect. (the right channels registry settings are preserved.) register address bit label default description 0011 pcm control 5 atc 0 attenuator control mode: 0: right channels use right attenuation 1: right channels use left attenuation table 8 attenuation control select bckin polarity by default, lrcin and din are sampled on the rising edge of bckin and should ideally change on the falling edge. data sources which change lrcin and din on the rising edge of bckin can be supported by setting the bcp register bit. setting bcp to 1 inverts the polarity of bckin to the inverse of that shown in figure 7, figure 8, figure 9, figure 10 and figure 11 register address bit label default description 0011 pcm control 6 bcp 0 bckin 0: normal polarity 1: inverted polarity table 9 bckin polarity control output phase reversal the rev register bit controls the phase of the output signal. setting the rev bit causes the phase of the output signal to be inverted. register address bit label default description 0011 pcm control 7 rev 0 analogue output phase 0: normal 1: inverted table 10 output phase control
wm8718 production data w pd rev 4.3 november 2006 23 digital audio interface control registers the wm8718 has a fully featured pcm digital audio interface whose interface format is selected via the fmt [1:0] and iwl[1:0] register bits in register m3. register address bit label default description 0010 format control 1:0 iwl[1:0] 00 interface format select 0010 format control 3:2 fmt[1:0] 00 interface format select table 11 interface format controls fmt[1] fmt[0] iwl[1] iwl[0] audio interface description (note 1) 0 0 0 0 16 bit right justified mode 0 0 0 1 20 bit right justified mode 0 0 1 0 24 bit right justified mode 0 0 1 1 not available 0 1 0 0 16 bit left justified mode 0 1 0 1 20 bit left justified mode 0 1 1 0 24 bit left justified mode 0 1 1 1 32 bit left justified mode 1 0 0 0 16 bit i 2 s mode 1 0 0 1 20 bit i 2 s mode 1 0 1 0 24 bit i 2 s mode 1 0 1 1 32 bit i 2 s mode 1 1 0 0 16 bit dsp mode 1 1 0 1 20 bit dsp mode 1 1 1 0 24 bit dsp mode 1 1 1 1 32 bit dsp mode table 12 audio data input format note: 1. in all modes, the data is signed 2's complement. the digital filters always input 24-bit data. if the dac is programmed to receive 16 or 20 bit data, the wm8718 pads the unused lsbs with zeros. if the dac is programmed into 32-bit mode, the 8 lsbs are treated as zero.
wm8718 production data w pd rev 4.3 november 2006 24 digital filter characteristics parameter symbol test conditions min typ max unit passband edge -3db 0.487fs passband ripple f < 0.444fs 0.05 db stopband attenuation f > 0.555fs -60 db table 13 digital filter characteristics dac filter responses -120 -100 -80 -60 -40 -20 0 0 0.5 1 1.5 2 2.5 3 response (db) frequency (fs) figure 14 dac digital filter frequency response ? 44.1, 48 and 96khz -0.2 -0.15 -0.1 -0.05 0 0.05 0.1 0.15 0.2 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 response (db) frequency (fs) figure 15 dac digital filter ripple ? 44.1, 48 and 96khz -80 -60 -40 -20 0 0 0.2 0.4 0.6 0.8 1 response (db) frequency (fs) figure 16 dac digital filter frequency response ? 192khz -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 response (db) frequency (fs) figure 17 dac digital filter ripple ? 192khz
wm8718 production data w pd rev 4.3 november 2006 25 digital de-emphasis characteristics -10 -8 -6 -4 -2 0 0 2 4 6 8 10 12 14 16 response (db) frequency (khz) figure 18 de-emphasis frequency response (32khz) -3 -2.5 -2 -1.5 -1 -0.5 0 0.5 1 0 2 4 6 8 10 12 14 16 response (db) frequency (khz) figure 19 de-emphasis error (32khz) -10 -8 -6 -4 -2 0 0 5 10 15 20 response (db) frequency (khz) figure 20 de-emphasis frequency response (44.1khz) -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0 5 10 15 20 response (db) frequency (khz) figure 21 de-emphasis error (44.1khz) -10 -8 -6 -4 -2 0 0 5 10 15 20 response (db) frequency (khz) figure 22 de-emphasis frequency response (48khz) -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 0 5 10 15 20 response (db) frequency (khz) figure 23 de-emphasis error (48khz)
wm8718 production data w pd rev 4.3 november 2006 26 typical performance -120 -86 -118 -116 -114 -112 -110 -108 -106 -104 -102 -100 -98 -96 -94 -92 -90 -88 d b r a -160 +0 -150 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 dbv figure 24 thd+n versus input amplitude (@ 1khz, 'a' weighted) -120 +0 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b r a 30 20k 50 100 200 500 1k 2k 5k 10k hz figure 25 thd+n versus frequency ('a' weighted)
wm8718 production data w pd rev 4.3 november 2006 27 applications information recommended external components ? 20 lead ssop figure 26 external components diagram ? 20 lead ssop
wm8718 production data w pd rev 4.3 november 2006 28 recommended external components ? 24 lead qfn figure 27 external components diagram ? 24 lead qfn recommended external components values component reference suggested value description c4 and c7 10 f de-coupling for dvdd and avdd c1 and c6 0.1 f de-coupling for dvdd and avdd c5 0.1uf de-coupling for vrefp positive dac reference supply c2 0.1 f c3 10 f reference de-coupling capacitors for vmid pin. c8 10 f filtering for vrefp. omit if avdd low noise. r1 33 ? filtering for vrep. use 0 ? if avdd low noise. table 14 external components description
wm8718 production data w pd rev 4.3 november 2006 29 recommended analogue low pass filter for pcm data format (optional) wm8718 loutn loutp r1 2k7 ? r2 2k7 ? r3 3k ? r5 r4 r6 2k7 ? 2k7 ? 3k ? c1 680pf c2 220pf c3 680pf c4 220pf - + op left routn routp other channel right figure 28 recommended low pass filter (optional) note: 1. additional information on suitable output filters can be found in application note wan0171.
wm8718 production data w pd rev 4.3 november 2006 30 package dimensions ? 20 lead ssop notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. body dimensions do not include mold flash or protrusion, not to exceed 0.20mm. d. meets jedec.95 mo-150, variation = ae. refer to this specification for further details. dm0015.c ds: 20 pin ssop (7.2 x 5.3 x 1.75 mm) symbols dimensions (mm) min nom max a ----- ----- 2.0 a 1 0.05 ----- ----- a 2 1.65 1.75 1.85 b 0.22 0.30 0.38 c 0.09 ----- 0.25 d 6.90 7.20 7.50 e 0.65 bsc e 7.40 7.80 8.20 5.00 5.30 5.60 l 0.55 0.75 0.95 ref: a a2 a1 seating plane -c- 0.10 c 10 1 d 11 20 e b e1 e - jedec.95, mo 150 0 o 4 o 8 o e 1 l 1 1.25 ref c l gauge plane 0.25 l 1
wm8718 production data w pd rev 4.3 november 2006 31 package dimensions ? 24 lead qfn dm045.a fl: 24 pin qfn plastic package 4 x 4 x 0.9 mm body, 0.50 mm lead pitch index area (d/2 x e/2) top view d e 4 notes: 1. dimension b applies to metallized terminal and is measured between 0.15 mm and 0.30 mm from terminal tip. 2. falls within jedec, mo-220, variation vggd-2. 3. all dimensions are in millimetres. 4. the terminal #1 identifier and terminal numbering convention shall conform to jedec 95-1 spp-002. 5. coplanarity applies to the exposed heat sink slug as well as the terminals. 6. refer to applications note wan_0118 for further info rmation regarding pcb footprints and qfn package soldering. 7. depending on the method of lead termination at the edge of the package, pull back (l1) may be present. 8. this drawing is subject to change without notice. a3 g t h w b exposed lead half etch tie bar dimensions (mm) symbols min nom max note a a1 a3 0.80 0.90 1.00 0.05 0.02 0 0.20 ref b d d2 e e2 e l 0.30 0.18 4.00 2.80 2.70 2.55 0.50 bsc 0.30 0.40 0.50 2 2 4.00 2.80 2.70 2.55 0.10 aaa bbb ccc ref: 0.15 0.10 jedec, mo-220, variation vggd-2. tolerances of form and position 0.25 h 0.1 0.213 g t 0.1 w 0.2 detail 1 detail 2 a 6 1 13 18 24 19 12 e d2 b 7 1 b c bbb m a bottom view c aaa 2 x c aaa 2 x 1 c a3 seating plane detail 2 a1 c 0.08 c ccc a 5 side view l l1 l1 0.15 0.03 7 exposed ground paddle 6 detail 1 0.32mm 45 degrees exposed ground paddle e datum detail 2 terminal tip e/2 1 r e2 see detail 2
wm8718 production data w pd rev 4.3 november 2006 32 important notice wolfson microelectronics plc (?wolfson?) products and services are sold subject to wolfson?s terms and conditions of sale, delivery and payment supplied at the time of order acknowledgement. wolfson warrants performance of its products to the specifications in effect at the date of shipment. wolfson reserves the righ t to make changes to its products and specifications or to discontinue any product or service without notice. customers should therefore obtain the latest version of relevant information from wolfson to verify that the information is current. testing and other quality control techniques are utilised to the extent wolfson deems necessary to support its warranty. specific testing of all parameters of each device is not necessarily performed unless required by law or regulation. in order to minimise risks associated with customer applications, the customer must use adequate design and operating safeguards to minimise inherent or procedural hazards. wolfson is not liable for applications assistance or customer product design. the customer is solely responsible for its selection and use of wolfson products. wolfson is not liable for such selection or use nor for use of any circuitry other than circuitry entirely embodied in a wolfson product. wolfson?s products are not intended for use in life support systems, appliances, nuclear systems or systems where malfunction can reasonably be expected to result in personal injury, death or severe property or environmental damage. any use of products by the customer for such purposes is at the customer?s own risk. wolfson does not grant any licence (express or implied) under any patent right, copyright, mask work right or other intellectua l property right of wolfson covering or relating to any combination, machine, or process in which its products or services might be or are used. any provision or publication of any third party?s products or services does not constitute wolfson?s approval, licence, warranty or endorsement thereof. any third party trade marks contained in this document belong to the respective thir d party owner. reproduction of information from wolfson datasheets is permissible only if reproduction is without alteration and is accompanied by all associated copyright, proprietary and other notices (including this notice) and conditions. wolfson is not liable for any unauthorised alteration of such information or for any reliance placed thereon. any representations made, warranties given, and/or liabilities accepted by any person which differ from those contained in this datasheet or in wolfson?s standard terms and conditions of sale, delivery and payment are made, given and/or accepted at that person?s own risk. wolfson is not liable for any such representations, warranties or liabilities or for any reliance placed the reon by any person. address: wolfson microelectronics plc 26 westfield road edinburgh eh11 2qb united kingdom tel :: +44 (0)131 272 7000 fax :: +44 (0)131 272 7001 email :: sales@wolfsonmicro.com

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